(1) Field of the Invention
The invention relates to an I/O buffer. More specifically, the invention relates to improving the leakage currents characteristics of the p-output path of a five volt tolerant I/O buffer.
(2) Related Art
Input/output (I/O) buffers are generally well-known in the art. Early semiconductor processes were designed to operate in the voltage range of zero to five volts. Lower power processes have been developed such that some existing semiconductor processes are designed to use lower voltage ranges. For example, CMOS technologies frequently operate between the power supply voltage (V.sub.cc) of 3.3 volts and ground. Because such circuits are often used in an environment having components which still require a 5 volt range, it is necessary to devise a lower voltage circuit that operates in a higher voltage environment. Different voltage ranges are increasingly common, and voltage protection is necessary any time a lower voltage chip resides in a higher voltage environment. For example, if the CMOS chipset shares a bus with a typical dynamic random access memory (DRAM) interface, when the chipset tri-states its I/O buffer and samples the bus, signals may be driven back at five volts. Thus, the I/O buffer must be designed to tolerate five volts without a functionality or reliability problem. To do this, it is desirable to prevent the five volts from passing through the I/O buffer to the chipset itself.
FIG. 1 shows a prior art circuit employed in an output buffer to accomplish the necessary protection and reliability in a five volt environment In the p-output path, p-predriver 1 drives a signal into passgate 14 which is composed of an n-type transistor 8 and p-type transistor 9. N-type transistor 8 has a gate coupled to a supply voltage V.sub.cc while its other two terminals are connected to the corresponding terminals of the p-type transistor 9. The drains of transistors 8 and 9 are coupled to the gate 10 of p-driver 6 which is also a p-type transistor. The source terminal of the p-driver is connected to a peripheral power supply (V.sub.ccp), and the drain is connected to pad 5. V.sub.ccp is nominally the same voltage as V.sub.cc, however, because of noise considerations, it is common practice to employ a separate power rail for the p-driver and peripherals. One could, of course, couple the p-driver 6 to V.sub.cc instead. One of ordinary skill in the art will also recognize the p-type transistors have a fourth terminal providing a necessary N-well bias. N-well biasing is performed in a manner consistent with high voltage tolerant design. This fourth terminal is omitted throughout for clarity.
One of ordinary skill in the art will recognize that the transistors are symmetric. Stated differently, defining a particular terminal to be a source or drain is arbitrary as the source or drain is actually defined by the voltage relative to the gate voltage of a particular transistor at a particular time. Taking the p-driver 6 as an example, if the voltage at gate 10 is at least a threshold voltage (V.sub.T) below one of the other terminals, the highest voltage terminal will be the source. Thus, if, for example, pad 5 is at five volts and the voltage at gate 10 is V.sub.T less than 5 volts, the pad terminal of p-driver 6 becomes the source and the drain is connected to V.sub.ccp, thereby creating a DC current sink in the power supply. Conversely, under normal operation, the source will be the terminal connected to V.sub.ccp.
Resistors 11 and 12 provide electrostatic discharge (ESD) protection for the circuit. High voltage bias transistor 7 is used to prevent the DC current sink in the power supply discussed above in connection with the p-driver. The gate of the high voltage bias transistor is tied to V.sub.cc. Accordingly, when the pad voltage exceeds V.sub.cc by V.sub.T, the pad voltage appears at the gate of the p-driver. Because the pad voltage appears at the gate 10 of the p-driver 6, there is not a V.sub.T drop between the pad and the gate of the p-driver, the p-driver remains off and no current is sourced to V.sub.cc through the p-driver. Additionally, because gate 13 of the p-transistor 9 of the passgate 14 is connected to the pad, the pad voltage appears at the gate 13 of the p-transistor 9 and keeps the p-transistor 9 turned off. This prevents a high voltage signal from being driven back into the p-predriver 1 and further into the internal components (not shown).
N-type transistors 3 and 4 form an n-driver stack and are driven by the n-predriver 2. N-transistor 4 is gate coupled to the N-predriver 2 and source coupled to V.sub.ssp. V.sub.ssp is typically ground. Transistor 3 is gate coupled to V.sub.cc. Accordingly, the maximum voltage that can appear at the intermediate node in the stack is V.sub.cc -V.sub.T. Thus, the high voltage is effectively stopped at the passgate and in the n-driver stack.
In the course of normal operation, to drive the pad 5 to V.sub.ccp, the gates of the n-driver 4 and p-driver 6 must be driven low. To drive the pad 5 low, both drivers' gates must be driven high. To float the pad 5 and go into tri-state, both drivers 4, 6 must be turned off. Therefore, the p-driver gate 10 must be driven high, and the gate of the n-driver 4 must be driven low. This creates an indeterminate condition at the pad 5. When in tri-state, it is often desirable to know the state of the pad 5, e.g., it is desirable to pull the pad 5 high or pull the pad 5 low so that when the pad 5 is not being driven, it is in a known state. One way this is typically done is by using a weak resistor as a pull-down resistor 15 or pull-up resistor (not shown). A pull-down resistor 15 from the pad to ground is shown for illustration. Leakage current from the p-driver 6 can prevent the desired pull-down. Moreover, if the p-driver 6 leaks, this leakage represents a power waste, both in terms of the current sourced by the p-driver 6, but also because external devices have to drive back that much harder against this leakage current to successfully drive the pad 5. While power waste is undesirable in any event, it can be devastating in low power systems, including mobile systems.
The prior art circuit exhibits leakage in the p-output path under certain conditions. Specifically, failure conditions exist when the pad 5 is driven to a logic 1 which implies that the gate of the n-driver 4 is low and the p-driver gate 10 is low. Therefore, 3.3 volts appear at the pad 5, and the same 3.3 volts appear at the p-gate 13 of the passgate 14. Thus, the p-transistor 9 of the passgate 14 is turned off. However, the n-transistor 8 has no trouble sourcing a zero volt signal to the gate 10 of the p-driver 6. Thus, the p-driver 6 is on, and the pad 5 is driven high. A problem occurs in the transition from a pad high condition to a tri-state. To float the pad 5, the gate 10 of the p-driver 6 must be driven high to shut the p-driver 6 off. Unfortunately, one can only drive a voltage up to a V.sub.cc -V.sub.T through the n-transistor 8 of the passgate 14. The p-transistor 9 of the passgate 14 remains off because the 3.3 volts of the pad 5 continue to appear at its gate 13. Since the maximum voltage that can be driven through the n-transistor 8 is less than the voltage required to turn the p-driver 6 off, a leakage path exists from V.sub.ccp through p-driver 6 through the pull-down resistor 15 to ground. Therefore, a leakage current results until the voltage at the pad 5 is reduced enough to allow the p-transistor 9 of the passgate 14 to turn on, and 3.3 volts can be sourced to a gate of the p-driver 6 shutting the p-driver 6 off. Unfortunately, a weak pull-down resistor may not be strong enough to drag the pad 5 low enough to turn the p-transistor 9 of the passgate 14 on.
To reduce this unnecessary power drain and to ensure that the pad 5 can be placed in a known state when not driven, it would be desirable to be able to prevent this leakage current while still protecting the internal circuitry from high voltages of external drivers.